Validation of Memristor-Based Entropy Sources Using an Automated TRNG Testing Framework
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Memristive devices have emerged as promising candidates as entropy source due to their intrinsic stochastic dynamics, including switching variability, filament formation, and random telegraphic noise. These phenomena can be exploited to implement true random number generators (TRNGs) suitable for security-critical applications in Internet of Things (IoT) systems. However, a key challenge in this context is not only the design of entropy sources, but also their rigorous, reproducible, and efficient validation under standardized statistical criteria. This work presents an automated framework for the statistical evaluation of random number generators, reoriented here as a validation tool for memristor-based TRNGs. The platform integrates a web-based architecture capable of executing the complete NIST SP 800-22 statistical test suite, enabling immediate analysis of binary sequences generated by experimental devices. Through a set of REST interfaces, the system allows both manual and programmatic interaction, supporting concurrent execution and real-time reporting of results. The primary contribution of this work lies in decoupling entropy source development from the complexity of statistical validation. By providing near real-time feedback on randomness quality, the framework significantly reduces the overhead associated with test execution, data processing, and result interpretation. This enables researchers to focus on the underlying physical mechanisms of memristive devices, systematically exploring different operating regimes, material properties, and noise dynamics that can be used as entropy sources. As a proof of concept, the framework is deployed in an IoT-oriented environment where random sequences are continuously validated prior to their use in cryptographic operations. The system successfully differentiates between deterministic and true random sources, demonstrating its effectiveness as a diagnostic tool. The proposed approach facilitates rapid iteration in the design and characterization of memristor-based TRNGs, accelerating their integration into secure hardware architectures.