Resistive random-access memories (ReRAM) are promising candidates for next-generation non-volatile memory and in-memory computing applications, thanks to their scalability, low power consumption, and capability for analog resistance tuning. However, their adoption in circuit-level design remains challenging due to the inherently stochastic nature of the switching process and the difficulty of representing reliable multilevel operation within compact, SPICE-compatible models. In this work, we propose a compact probabilistic ReRAM model that addresses both challenges within a unified circuit-level framework. The model is structured around three main components: a voltage-dependent probabilistic switching block, a history-dependent state evolution block, and a transport block governing the device current (Fig. 1). Switching dynamics are described through SET and RESET probabilities calibrated from experimental data, enabling an efficient statistical representation of filamentary behavior. A state variable tracks the progressive modification of the most active region of the conductive filament, allowing the model to capture memory effects, intermediate resistance states, and gradual resistance modulation. The transport block employs closed-form expressions to reproduce both low- and high-resistance regimes, ensuring numerical robustness and simulation efficiency. The model is implemented in spice and calibrated using experimental data from HfO₂-based 1T1R ReRAM devices. It successfully reproduces gradual resistance tuning, multilevel programming, and the statistical distributions of key switching parameters. In particular, it captures the cumulative evolution of resistance under successive programming pulses and the impact of variability on final programmed states. By jointly accounting for multilevel operation, cycle-to-cycle variability, and device-to-device dispersion, the proposed model enables realistic, variability-aware simulations of ReRAM-based devices and arrays, making it a valuable tool for the design and evaluation of memory, analog computing, and neuromorphic circuits.