Memristor-based neural networks have emerged as a promising platform for Energy-efficient neuromorphic computing, enabling in-memory processing through crossbar architectures. However, the performance of these systems is strongly affected by device-level non-idealities such as nonlinear conductance updates, limited dynamic range, and discrete conductance states. In this work, we present a systematic study of artificial neural networks implemented with realistic memristor models and trained using the hardware-friendly Manhattan update rule. We analyze both single-layer perceptrons and multilayer perceptrons on benchmark classification tasks, evaluating the impact of potentiation/depression nonlinearity, conductance window, and resolution on learning accuracy and convergence. We introduce a nonlinearity index to quantify deviations from ideal device behavior and identify tolerance thresholds required to preserve performance. Our results show that deeper architectures impose stricter constraints on device linearity, while increased conductance resolution improves training stability. Additionally, we propose a simplified training strategy in which only one device per differential synapse is actively updated, reducing redundant conductance programming. This approach achieves substantial energy savings—up to ~45% in multilayer networks—while maintaining comparable accuracy. These findings highlight the importance of device–algorithm co-design and provide practical guidelines for the development of scalable, low-power memristive hardware for edge artificial intelligence applications.